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INTEGRATED CIRCUITS
DATA SHEET
SAA2003 Stereo filter and codec
Preliminary specification File under Integrated Circuits, IC01 May 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Stereo filter and codec
FEATURES * Single-chip stereo filter and codec * Wide operating voltage range: 2.7 to 5.5 V * Low-power consumption: 98 mW; 3.0 V * Sleep mode for low power and low Electromagnetic Interference (EMI) * Transparent serial audio data mode in sleep * IEC 958 digital output * Peak level detector for start of track detection or VU meter * Versatile fade processor; slow/fast fade, mute, 12 dB attenuation * Serial audio interface for I2S or EIAJ formats * Error concealment * Three-wire L3 bus microcontroller interface * Three sample rates: - 32 kHz - 44.1 kHz - 48 kHz * Internal or external clock source * Three programmable outputs * Small surface mounted package (SOT307). ORDERING INFORMATION EXTENDED TYPE NUMBER SAA2003H Note PACKAGE PINS 44 PIN POSITION QFP(1) MATERIAL plastic GENERAL DESCRIPTION
SAA2003
The SAA2003 performs the sub-band filtering and audio frame codec functions in the Precision Adaptive Sub-band Coding (PASC) system. It can be used as a stand-alone decoder for playback only applications, but requires the addition of an Adaptive Allocation and Scale Factor processor (SAA2013) in order to perform PASC encoding in a DCC record system.
CODE SOT307
1. When using reflow soldering it is recommended that the Dry Packing instructions in the "Quality Reference Pocketbook" are followed. The pocketbook can be ordered using the code 9398 510 34011.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
BLOCK DIAGRAM
SAA2003
handbook, full pagewidth
X22OUT X24OUT CLK24 FS256 X22IN X24IN CLK22 X256 6 5 10 9 4 11 37 38
VDD1 V DD2 VDD3 28 7 39 32 MUTEDAC 31 ATTDAC DEEMDAC
CLOCK GENERATOR TEST0 TEST1 IECOP 19 20 29 IEC 958 OUTPUT FS128 6.15 MHz FS256 SBMCLK
30
25 SBWS WS SCK SD1 SD2 34 33 36 35 BASEBAND SERIAL INTERFACE AND PEAK DETECTOR SUBBAND SERIAL INTERFACE 24 23 22 26 SBCL SBDA SBDIR SBEF
SAA2003
STEREO SUBBAND FILTER PROCESSOR
PASC CODEC PROCESSOR
21 FILTERED DATA INTERFACE MICROCONTROLLER INTERFACE AND CONTROL 13 12
URDA RESET SLEEP
27
8
40
43
2 FDCL
3
44 FDAO
1
17 LTCNT0
18
14
15
16
41
42
MBD618
V SS1 V SS2 V SS3
L3DATA
L3MODE
SYNCDAI
FSYNC
FDWS
FDAI
LTCNT1
L3CLK
FDIR
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
PINNING SYMBOL FDAI FDCL FDWS CLK22 X22OUT X22IN VDD2 VSS2 X24OUT X24IN CLK24 SLEEP RESET L3DATA L3CLK L3MODE LTCNT0 LTCNT1 TEST0 TEST1 URDA SBDIR SBDA SBCL SBWS SBEF VSS1 VDD1 IECOP DEEMDAC ATTDAC MUTEDAC SD2 SD1 SCK WS X256 FS256 VDD3 VSS3 May 1994 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 filtered data bit clock filtered data word select 22.5792 MHz buffered clock output 22.5792 MHz crystal output 22.5792 MHz crystal input supply voltage (clock oscillator) supply ground (clock oscillator) 24.576 MHz crystal output 24.576 MHz crystal input 24.576 MHz buffered clock output sleep mode; device inactive device reset 3-wire interface; serial data 3-wire interface; bit clock 3-wire interface; mode control LT interface; control bit 0 LT interface; control bit 1 test mode select test mode select unreliable data flag from drive processor sub-band data direction sub-band serial data sub-band bit clock sub-band word select sub-band error flag from drive processor digital supply ground digital supply voltage IEC 958 digital audio output DAC control or general purpose output DAC control or general purpose output DAC control or general purpose output serial audio data to DAC serial audio data to/from DAIO and DAC serial audio data bit clock serial audio data word select master audio clock from external source master audio clock at 256 times sample frequency supply voltage (FS256) supply ground (FS256) 4 DESCRIPTION filtered data input from SAA2013
SAA2003
TYPE I O O O O I - - O I O I I I/O I I I I I I I I I/O I/O I/O I - - O O O O O I/O I/O I/O I O - -
Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
SYMBOL FDIR SYNCDAI FSYNC FDAO
PIN 41 42 43 44
DESCRIPTION filter direction; encode or decode settings synchronization for DAIO sub-band 0 sample synchronization for SAA2013 filtered data output to SAA2013
TYPE O O O O
42 SYNCDAI
43 FSYNC
38 FS256
44 FDAO
39 VDD3
40 VSS3
41 FDIR
37 X256
35 SCK
FDAI FDCL FDWS CLK22 X22OUT X22IN VDD2 VSS2 X24OUT
1 2 3 4 5 6 7 8 9
34 SD1
36 WS
33 SD2 32 MUTEDAC 31 ATTDAC 30 DEEMDAC 29 IECOP
SAA2003
28 VDD1 27 VSS1 26 SBEF 25 SBWS 24 SBCL 23 SBDA
MBD619
X24IN 10 CLK24 11
TEST1 20
URDA 21
SLEEP 12
RESET 13
L3DATA 14
L3CLK 15
L3MODE 16
LTCNT0 17
LTCNT1 18
Fig.2 Pin configuration.
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SBDIR 22
TEST0 19
handbook, full pagewidth
May 1994
L analog output R baseband I 2S L analog input R ADC SAA7366 filtered I2 S ADAS3 SAA2013 ADAPTIVE ALLOCATION IEC958 DIGITAL AUDIO I/O TDA1315 search data analog CC L output analog CC R output SFC3 SAA2003 STEREO FILTER CODEC DAC TDA1305 sub-band I 2S WRAMP TDA1381 WRITE AMP. FIXED HEAD RDAMP TDA1380 READ AMP. RAM 41464 BUFFER 64K x 4 speed control CAPSTAN DRIVE DRP SAA2023 OR SAA3323 DRIVE PROCESSOR TAPE
FUNCTIONAL DESCRIPTION
Philips Semiconductors
Stereo filter and codec
6
AUDIO IN/OUT
MECHANICS DRIVERS
PASC PROCESSOR
TAPE DRIVE PROCESSING
detect switch
SYSTEM MICROCONTROLLER
Preliminary specification
SYSTEM CONTROL
MBD620
SAA2003
Fig.3 DCC system block diagram.
Philips Semiconductors
Preliminary specification
Stereo filter and codec
PASC processor The PASC processor is a dedicated Digital Signal Processor (DSP) engine which efficiently codes digital audio data at a bit rate of 384 kbits/s without affecting the sound quality. This is achieved using an efficient adaptive data notation and by only encoding the information which can be heard by the human ear. The audio data is split into 32 equal sub-bands during encoding. For each of the sub-bands a masking threshold is calculated. The samples from each of the sub-bands are included in the PASC data with an accuracy that is determined by the available bit-pool and by the difference between the signal power and the masking threshold for that sub-band. The stereo filter codec performs the splitting (encoding) and reconstruction (decoding), including the necessary formatting functions. During encoding, the adaptive allocation and scaling circuit calculates the required accuracy (bit allocation) and scale factors of the sub-band samples. ENCODING (SEE FIG.4) The incoming serial audio data is filtered into 32 sub-bands for left and right (I and II) channels using the stereo filter part of the SAA2003. A PASC frame is made up of left and
SAA2003
right (I and II) audio data for 12 samples from each of the 32 sub-bands, a total of 768 audio samples. For every PASC frame the SAA2013 calculates a bit allocation and scale factor table which is transferred to the SAA2003. All the samples in a frame are scaled in accordance with the scale factor calculated by the SAA2013. Once scaled the samples are re-quantized to reduce the number of bits to correspond with the allocation table calculated by the SAA2013. Synchronization, allocation and scale factor information is then added to provide a fully encoded PASC data signal. These frames of data are then sent to the drive processor IC (SAA2023 or SAA3323). DECODING (SEE FIG.5) In decoding mode the SAA2003 synchronizes and recovers frames of data from the drive processor. The recovered allocation data and the scale factors are used to correctly re-quantize and re-scale the PASC sub-band samples. The decoded sub-band samples, which are represented in 24-bits two's complement notation, are reconstructed by the sub-band filters into a single complete digital audio signal.
handbook, full pagewidth
from SAA2013
ALLOCATION AND SCALE FACTOR INFORMATION TABLE
allocation information and scale factor indices
SYNC AND CODING INFORMATION baseband samples SUB-BAND FILTER sub-band samples SCALING AND QUANTI ZATION
FORMATTER
quantified samples
PASC OUTPUT DATA
MLB764
Fig.4 Encoding mode.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
handbook, full pagewidth
sync/coding
CONTROL
allocation scale factor PASC data input DE- FORMATTER quantified samples
SCALE FACTOR ARRAY AND ALLOCATION sub-band samples
DE-QUANTIZATION
MULTIPLY
OUTPUT CONTROL
SUB-BAND FILTER
baseband samples
MEA804 - 1
Fig.5 Decoding mode.
Crystal oscillators The recommended crystal oscillator configuration is shown in Fig.6. The specified component values only apply to crystals with a low equivalent series resistance of <40 .
C2 33 pF 22.5792 MHz X1 R1 1 M
X22IN
40
C1 33 pF
X22OUT R2 220 X24IN
41 42
SAA2003
C3 33 pF
24.576 MHz X2
R4 1 M X24OUT R3 1 k
MBD621
43
C4 33 pF
Fig.6 Crystal oscillator components.
System reset Reset must be active from system power-up for >1 ms. Reset must also be active for >1 ms after the falling edge of sleep as shown in Fig.7.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
handbook, full pagewidth
MODE 1 t1
MODE 2 t2
MODE 3 t3
MODE 4
STANDBY
RESET
CLK24/CLK22
ACTIVE
STATIC
ACTIVE
I/O's
ACTIVE
ACTIVE
MBD622
Fig.7 Reset and sleep timing.
Table 1
Reset and sleep timing modes (see Fig.7). DESCRIPTION standby stage 1; clocks still running standby mode; clocks stopped clocks running; reset active normal operational mode t1 t2 t3 - TIMING 0 1 - MIN. 400 - - - - MAX. ns ns ms UNIT
MODE MODE1 MODE2 MODE3 MODE4 Sleep mode
A HIGH input applied to the SLEEP pin halts all internally generated clock signals. If the transparent mode of the serial audio interface is set before entering sleep, the data at the X256 external clock input is sent to the FS256 output and the data at SD1 input is sent to the SD2 output. If transparent mode is not set, these two outputs are high impedance during sleep mode. The IECOP pin is set to high impedance during sleep mode, unless the transparent mode is selected and WS-SEL is set.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
Table 2 Transparent mode function in sleep. PIN FS256 FS256 SD2 SD2 IECOP IECOP IECOP Notes 1. Transparent mode is controlled by bit 3 of the serial audio data interface mode control register. 2. WS-SEL is controlled by bit 3 of the codec extended settings register. Serial audio interface The signals between the SAA2003 and the serial audio input/output are shown in Table 3. Table 3 Interface signals between SAA2003 and serial audio input/output. PIN WS SCK SD1 SD2 FDIR IECOP INPUT/OUTPUT bi-directional bi-directional bi-directional output output output FUNCTION audio data word select audio data bit clock serial audio data to/from DAIO and ADC audio serial data to DAC PASC mode encode/decode alternative serial data word select for SD2 fs TRANSPARENT MODE(1) 1 0 1 0 0 1 1 WS-SEL(2) X X X X X 0 1 FS256 high impedance SD1 high impedance high impedance high impedance WS
SAA2003
PIN FUNCTION
FREQUENCY 64fs - - - -
The word select (WS) line indicates the channel being transmitted (either left or right; I or II) and is equal in frequency to the sampling frequency (fs). Operating at a frequency of 64 x fs, the bit clock (SCK) dictates that each WS period contains 64 SD1 or SD2 data bits. Of these bits a maximum of 36 are used to transfer data (samples may have a length up to 18 bits). Samples are transferred most significant bit (MSB) first. Both WS and SD1/SD2 change state at the negative edge of SCK. The serial audio data is transferred between the SAA2003 and the input/output using either the standard I2S (default) as shown in Fig.8 or the EIAJ format as shown in Fig.9.
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0 SCL 1 2 3 17 18 31 32 33 34 35 49 50 63 0 1 2 SWS left channel data right channel data SD1/ SD2 MSB LSB MSB LSB MSB
Philips Semiconductors
Stereo filter and codec
a.
0 SCL 1 2 3 12 13 14 15 16 17 18 19 28 29 30 31 0 1 2
11
SWS SD1/ SD2
left channel data
right channel data
MSB
LSB MSB
LSB MSB
MBD623
b. Preliminary specification
SAA2003
a. Master and slave modes; 18 bits. b. Slave mode only; 16 bits.
Fig.8 Serial audio interface SD1/SD2; I2S data format.
May 1994
0 SCL 1 2 14 15 30 31 32 33 46 47 62 63 0 1 2 SWS left channel data right channel data SD1/ SD2 MSB MSB LSB MSB MSB LSB MSB
Philips Semiconductors
Stereo filter and codec
a. 12
SCL SWS SD1/ SD2 0 1 2 16 17 30 31 32 33 48 49 62 63 0 1 2
left channel data
right channel data
MSB
MSB
LSB
MSB
MSB
LSB
MSB
MBD624
b. Preliminary specification
SAA2003
a. Master mode; 18 bits. b. Master mode (EIAJ); 16 bits.
Fig.9 Serial audio interface SD1; EIAJ data format.
Philips Semiconductors
Preliminary specification
Stereo filter and codec
SERIAL AUDIO INTERFACE DATA FORMATS IN ENCODING MODE
SAA2003
In encoding mode, the serial audio data input for the PASC processor is taken from the SD1 pin. This data is scaled by the fade processor before being sent to the PASC processor. The output from the fade processor is sent in parallel to the SD2 output. Both I2S and EIAJ formats are supported. Table 4 Serial audio data interface formats in encoding mode. SD1 INPUT FORMAT I2S I2 S I2 S I2 S EIAJ(1) EIAJ(1) EIAJ(1) EIAJ(1) Note 1. If SD1 is used in EIAJ mode, and the data from SD2 is required, the IECOP can be re-programmed to provide a suitable I2S WS signal for SD2. The IEC 958 output is not available in this mode. SERIAL AUDIO INTERFACE DATA FORMATS IN DECODING MODE In decoding mode, the output from the PASC processor, connected via the fade processor, is present at both SD1 and SD2. Both I2S and EIAJ formats are supported. Table 5 SD1/SD2 output decoding formats. MASTER/SLAVE master slave master slave master master 18 bit 18 bit 16 bit 16 bit 18 bit 16 bit RESOLUTION(1) MASTER/SLAVE master slave master slave master slave master slave RESOLUTION 18 bit 18 bit 16 bit 16 bit 18 bit 18 bit 16 bit 16 bit I2S I2S I2S I2S I2S I2S I2S I2S FORMAT SD2 OUTPUT RESOLUTION 18 bit 18 bit 18 bit 16 bit 18 bit 18 bit 18 bit 18 bit
FORMAT I2S I2S I2S I2S EIAJ EIAJ Note
1. The sub-band filter performs rounding to 16 or 18 bits according to the operating mode of the interface. SERIAL AUDIO INTERFACE MODE CONTROL The operating mode of the interface is programmed by the extended settings registers as shown in Table 6.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
Table 6 A3 0 0 0 0 0 0 0 0 Extended settings register. A2 0 0 0 0 0 0 0 0 A1 1 1 1 1 1 1 1 1 A0 0 0 0 0 0 0 0 0 D3 X X X X X X 0 1 D2 X X X X 0 1 X X D1 X X 0 1 X X X X D0 0 1 X X X X X X MODE 16 bit operation; 16 bit rounding 18 bit operation; 18 bit rounding I2S data format EIAJ data format peak detector input SD1 peak detector input SD2
SAA2003
SD1/FS256 transparent mode disabled SD1/FS256 transparent mode enabled
Filtered data interface The filtered data interface transfers the sub-band filtered data between the stereo filter codec and adaptive allocation and scaling parts of the DCC chip-set, and consists of the signals as shown in Table 7. Table 7 Filtered data interface signals. PIN FDCL FDWS FDAO FDAI FDIR FSYNC INPUT/OUTPUT output output output input output output FUNCTION filtered data bit clock filtered data word select filtered data serial output filtered data serial input decode/encode control filtered data sync signal; band zero fs - - - - FREQUENCY 64fs
FILTERED DATA INTERFACE FORMAT The filtered data is transferred over the interface in accordance with the formats illustrated in Figs 10 and 11.
handbook, full pagewidth
channel
left 32 bits
right
FDWS
FDCL 1 FDAI/ FDAO bit : 2 3 MSB 2 2 2 1 2 0 0 2 0 1 0 0 LSB 2 3 MSB 2 2 2 1 2 0
MLB765
7 bits
Fig.10 Transfer of filtered data; SAA2003/SAA2013.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
32 bits SBWS
SBCL 1 SBDA bit : 00 01 MSB 0 2 0 3 1 0 1 1 1 2 1 3 1 4 1 5 LSB 11 67 MSB 1 8 1 9 2 0 2 1 2 2 15 bits 1
SBEF byte 0 byte 1 byte 2
MEA649 - 2
Fig.11 Transfer of sub-band PASC data.
Sub-band serial PASC interface The sub-band serial interface carries the PASC serial data stream between the stereo filter codec and the drive processor part of the DCC chip-set, and consists of the signals as shown in Table 8. Table 8 Sub-band serial PASC interface signals. INPUT/OUTPUT input input/output input/output input/output input input sub-band serial data sub-band bit clock sub-band word select sub-band data error flag unreliable data flag FUNCTION sub-band data direction control - - 768 kHz 12 kHz - - FREQUENCY
PIN SBDIR SBDA 1SBCL SBWS SBEF URDA
The SAA2003 generates SBWS and SBCL in both decode and encoding modes. In decode both signals can be set to inputs (slave mode) by bit 0 of the extended settings register. The filtered data interface timing is always derived from the 24.576 MHz clock, regardless of the audio sampling frequency. Table 9 A3 0 0 Extended settings register. A2 0 0 A1 0 0 A0 1 1 D3 X X D2 X X D1 X X D0 0 1 slave mode (default) master mode MODE
Stereo and 2-channel mono encoding modes are available. Stereo, joint stereo and 2-channel mono decoding modes are available. In decoding and encoding, 48 kHz, 44.1 kHz and 32 kHz sample frequencies can be used.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SUB-BAND SERIAL PASC INTERFACE DATA FORMAT The PASC data is transferred over the interface described above using the format shown in Fig.11. Each period of SBWS spans 64 periods of the bit clock, SBCL, of which 32 SBCL periods are used to transfer PASC data. The 32 data bits transferred in one period of SBWS make up a complete sub-band slot, as defined in the DCC standard. The first 16 data bits (0, 1, 2, .., 15) are transferred while SBWS is LOW, and the second 16 data bits (16, 17, 18, .., 31) are transferred while SBWS is HIGH. SBEF and URDA are generated by the drive processor during decode. The presence of the URDA flag causes the stereo filter codec to mute the audio output data, and lose audio frame synchronization. The direction of SBDA is controlled by the SBDIR input, which is connected to the drive processor. SYNCDAI signal SYNCDAI is a pulse of fixed duration which is generated by the SAA2003 when any of the following conditions occur: * Change of bit rate * Change of sampling frequency * Change from encode to decode and vice-versa * Change of FS256 clock source * Change of I2S bus master * Reset.
SAA2003
The SYNCDAI signal is used to synchronize the digital audio input/output interface. Audio peak level detector The peak level detector continuously encodes the maximum amplitude of the audio data samples for each audio channel until it is reset by the action of reading out the peak level data. The peak level data can be read by the SAA2013, and subsequently by the system microcontroller, or by the microcontroller directly when SAA2013 is not used. The peak level data is read via the L3 interface in status read mode. The first 16 bits of status read transfer the status bits of SAA2003. The following 32 bits contain the peak level data. The peak level detector is reset when the 32 bits of peak level data are read. In encode, the peak level detector can be used to monitor the data on either SD1 (pre-fade processor) or SD2 (post fade processor). In slave EIAJ input modes the peak detection is only possible on output SD2. In decode mode, SD1 must be selected for peak detector input data.
handbook, full pagewidth
L3MODE
L3CLK
L3DATA
8
15
0
7
16
17
30
31
32
33
46
47
MBD625
Fig.12 Peak level data format during status read.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
Audio fade processor
SAA2003
The fade processor is controlled by the system microcontroller. It achieves level control, or fading, by multiplying the audio samples with a 17 bit accuracy fade coefficient, which is selected by an 8-bit fade counter. The fade coefficients range from 0 to 1.0 according to a 14 cosine function. The attenuation for a particular fade count (FC) is given as follows: x FC Attenuation (dB) = - 20 log cos ----------------- ( dB ) where: 0 FC 255. 510 - In encode mode, audio samples are taken from input SD1 and scaled before sub-band filter processing, and sent to output SD2. In decode mode, audio samples are scaled following reconstruction by the sub-band filter, and sent to outputs SD1 and SD2. Table 10 Fade processor operating modes. MODE Fade rate Step down Step up Full scale Mute -12 dB increases attenuation by one increment reduces attenuation by one increment sets gain to unity, incrementing from current level automatically sets gain to zero, decrementing from current level automatically sets gain to -12 dB, decrementing or incrementing from current level automatically FUNCTION controls rate of automatic increments and decrements
FADE PROCESSOR MODE CONTROL The operating mode of the fade processor is controlled by two extended registers Table 11 Fade processor mode control. A3 0 0 0 0 0 0 0 0 0 0 A2 0 1 1 1 1 1 1 1 1 1 A1 1 0 0 0 0 0 0 0 0 0 A0 1 0 0 0 0 0 0 0 0 0 D3 P3 0 0 0 0 1 1 1 1 0 D2 P2 0 0 1 1 0 0 1 1 0 D1 P1 0 1 X X X X X X 0 D0 P0 1 0 0 1 0 1 0 1 0 set fade rate step down step up full scale slow full scale fast mute slow mute fast -12 dB slow -12 dB fast no action MODE
FADE RATE OPTION The fade rate can be set to either fast or slow modes. In fast mode the attenuation changes rate at one step per audio sample. In slow mode the rate of change of level is controlled by the fade rate bits P3 to P0. In slow mode, the fade counter is stepped up or down according to a clock derived from the WS pin.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
Table 12 Fade rate in slow and fast modes. TIME PER STEP (ms) MODE Fast Slow Slow Slow Slow Slow IEC 958 output P3 - 0 0 0 0 1 P2 - 0 0 0 1 1 P1 - 0 0 1 1 1 P0 32 kHz - 0 1 1 1 1 31.2 s 1.0 2.0 4.0 8.0 16.0 44.1 kHz 22.7 s 0.997 1.994 3.988 7.980 15.96 48 kHz 20.8 s 1.0 2.0 4.0 8.0 16.0 32 kHz 8.0 256 512 1024 2048 4096
SAA2003
TIME FOR 256 STEPS (ms) 44.1 kHz 5.8 255 511 1021 2043 4087 48 kHz 5.3 256 512 1024 2048 4096
The IECOP pin provides an output signal in accordance with the IEC 958/SPDIF digital audio interface format. The function of the IECOP pin is programmed by bit 3 of the codec extended settings register; see Table 13. Table 13 IECOP pin control. A3 0 0 A2 0 0 A1 0 0 A0 1 1 D3 0 1 D2 X X D1 X X D0 X X IECOP FUNCTION IEC 958 (default) I2S word select for SD2
The IECOP output will only function when the SAA2003 is in decode mode. The IECOP cannot be used when SAA2013 is present in the system, unless the SAA2013 is in sleep mode. The IECOP output is disabled and set to high impedance by a reset. L3 bus The L3 bus is a three-wire clock synchronous data bus common to all ICs in the DCC chip-set. It consists of the L3MODE, L3CLK and L3DATA connections. The bus has two operating modes: * Addressing mode; selects the IC for communication and sets type of transfer. * Data mode; is used to send and receive data and control settings. The L3MODE and L3CLK lines are driven by the system microcontroller and L3DATA is a bi-directional line. LTCNT0 and LTCNT1 must be left unconnected when L3 mode is used. For normal use in L3 mode, LTCNT0 and LTCNT1 are held HIGH by internal pull-up resistors. The SAA2003 responds to serial addresses as shown in Table 14. Table 14 SAA2003 serial addresses. D0(1) X Note 1. D0 and D1 are interpreted as LTCNT0 and LTCNT1 respectively. These two signals control the operation of the interface as given in Table 15. D1(1) X D2 0 D3 0 D4 0 D5 1 D6 0 D7 0
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
Table 15 Interface modes. D0/LTCNT0 0 1 0 1 D1/LTCNT1 0 0 1 1 MODE extended setting from microcontroller to SAA2003
SAA2003
allocation and scale factor information from SAA2013 to SAA2003 codec internal settings from microcontroller to SAA2003 codec status from SAA2003 to microcontroller and SAA2013 including peak level data
Table 16 Register address settings. A3 0 0 0 0 0 Note 1. These registers are write only, accessed using the protocol shown in Fig.13. A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0 codec external settings codec interface mode control serial audio interface mode control fade counter rate control fade counter control REGISTER(1)
andbook, full pagewidth
L3MODE
L3CLK
L3DATA
D0
D1
D2
D3
A0
A1
A2
A3
MBD626
Fig.13 Extended settings protocol.
Operation in LT mode LT interface mode can be selected by writing an extended settings word to the interface mode control register as shown in Table 17. Table 17 Interface mode control register. A3 0 0 A2 0 0 A1 0 0 A0 1 1 D3 X X D2 X X D1 1 0 D0 X X L3 mode (default) LT mode MODE
In LT mode the LTCNT0 and LTCNT1 pins are used, and the L3MODE pin becomes LTEN enable line. L3CLK becomes LTCLK, and L3DATA becomes LTDATA.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
Table 18 Summary of address registers. ADDRESS REGISTER BIT REGISTER 0 EXPLANATION external settings register 0 1 2 3 1 codec extended settings 0 1 2 3 2 serial audio mode control 0 1 2 3 3 4 5 to 15 fade processor fade rate fade processor control not used 0 to 3 0 to 3 - mute DAC attenuate DAC de-emphasis DAC clock OK hold mode slave receive mode L3/LT mode select comparator delay bypass WS/IEC 958 selection 18 bit operation I2S/EIAJ format peak detector input select transparent mode rate control, 0 to 15 fade command - DESCRIPTION
SAA2003
Codec internal settings and status The settings register is write only, and the status register is read only. The interface protocols for accessing these registers is shown in Figs 14 and 15.
handbook, full pagewidth
L3MODE
L3CLK
L3DATA
8
9
14
15
0
1
6
7
MBD627
Fig.14 Codec internal settings write transfer.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
30
31
32
33
46
MBD628
47
L3MODE
May 1994
L3DATA
L3CLK
Fig.15 Codec status read transfer. 21
8
15
0
7
16
17
Philips Semiconductors
Preliminary specification
Stereo filter and codec
The codec internal settings register is shown in Table 19. Table 19 Codec internal settings register formats. BITS 15 to 12 11 and 10 9 8 7 6 5 4 3 and 2 1 and 0 DESCRIPTION bit rate index sample frequency decode mode external FS256 2 channel mono mute sub-band filters external master I2S select channel I/II transparent bits emphasis indication encoding only encoding only encoding and decoding encoding and decoding encoding only encoding and decoding encoding and decoding decoding only encoding only encoding only
SAA2003
ENCODING/DECODING
Table 20 Codec status register formats. BITS 15 to 12 11 and 10 9 8 7 and 6 5 4 3 and 2 1 and 0 16 17 to 31 32 33 to 47 DESCRIPTION bit rate index sample frequency ready-to-receive not used sub-band mode synchronization clock OK transparent bits emphasis indication first channel identification first channel peak level; LSB first second channel identification second channel peak level; LSB first ENCODING/DECODING encoding and decoding encoding and decoding encoding and decoding - encoding and decoding decoding only encoding and decoding encoding and decoding encoding and decoding - - - -
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Preliminary specification
Stereo filter and codec
Average current consumption The average current consumption is shown in Fig.16.
SAA2003
handbook, halfpage
80
MBD640
I DD (mA) 60
40
20
0 2.5
3.5
4.5
V DD (V)
5.5
Fig.16 Average current consumption.
Timing diagrams
handbook, full pagewidth
T FS t fH t fL
FS256 t d1 SCK t cL Tc t h2 WS, SD1 and SD2 t d2
MBD629
t d1
t cH
Fig.17 Serial audio interface timing in decode; master mode.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
handbook, full pagewidth
T FS t fH t fL
FS256 t d1 SCK t cL Tc t h2 WS and SD2 t su SD1
MLB602
t d1
t cH
t h1
t d2
Fig.18 Serial audio interface timing in encode; master mode.
handbook, full pagewidth
Tc t cL t cH
SCK t su WS, SD1 t h2 SD1, SD2 t h1
T FS t FH FS256 t FL
td
MBD630
Fig.19 Serial audio interface timing; slave mode.
May 1994
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
handbook, full pagewidth
t SH
SYNCDAI t d1 WS, SCK (slave to master) t d2 WS, SCK (slave to master) t d3 t d4
SD1
MBD631
Fig.20 Serial audio master/slave timing.
andbook, full pagewidth
T FS t FH t FL
FS256 t d1 FDCL t cL t h2 FDWS, FDAO, FSYNC t d2 FDAI
MBD632
t d1
t cH Tc
t su
t h1
Fig.21 Filtered data interface timing.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
handbook, full pagewidth
sub-band # FDWS
0
1
2
29
30
31
0
1
2
3
FSYNC
MBD633
Fig.22 FSYNC output timing.
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t cL SCK t d1 SBWS, SBDA (encode) t d2
Tc t cH
t d4 t d3 SBWS (decode) t h1
t su1 SBDA
t h2 t su2 SBEF
MBD634
handbook, full pagewidth SBWS
SBCL
SBDA
0
1
2
3
4
5
6
7
8
9
10
11
12
L3DATA
MBD635
Fig.23 Sub-band PASC interface timing.
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
handbook, full pagewidth
t ML L3MODE t d1 L3CLK t su L3DATA (INPUT) t d2 t d3 t h1 t cH t cL t h2
L3DATA (OUTPUT)
MBD637
Fig.24 L3 bus timing; addressing mode.
handbook, full pagewidth
L3MODE t d1 L3CLK t su L3DATA (INPUT) t d3 t d2 L3DATA (OUTPUT) t ML L3MODE
MBD636
t cH
t cL
t h3
t h1
t d4 t h2
t d5
Fig.25 L3 bus timing; data transfer mode.
May 1994
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
handbook, full pagewidth
t SH
SYNCDAI t d2 t d1 FS256 CLOCK SOURCE internal t d5 t d4 FS256 CLOCK SOURCE external t d3 FDIR
MBD638
external
internal
Fig.26 Internal/external clock source transition timing.
Tc24 t c24L CLK24 tf tr t c24H
Tc22 t c22L CLK22 tf tr
MBD639
t c22H
Fig.27 CLK22 and CLK24 timing.
May 1994
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI II VO IO IDDQ Tstg Tamb Ves1 Ves2 Notes 1. The input voltage (VI) may not exceed 6.5 V. 2. Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. 3. Equivalent to discharging a 200 pF capacitor through a 2.5 H inductor. CHARACTERISTICS Tamb = -40 to 85 C; VDD = 2.7 to 5.5 V; unless otherwise specified. SYMBOL Supply VDD IDD supply voltage supply current VDD = 3.0 V VDD = 5.0 V sleep mode; VDD = 5.0 V VIL VIH ILI CI VIL VIH RI(pd) CI LOW level input voltage HIGH level input voltage input leakage current input capacitance VI = 0 to VDD 2.7 - - - 5.0 32.5 68.8 - 5.5 35.0 75.0 400 PARAMETER CONDITIONS MIN. TYP. PARAMETER supply voltage input voltage input current output voltage output current quiescent supply current storage temperature operating ambient temperature electrostatic handling electrostatic handling note 2 note 3 clocks stopped note 1 CONDITIONS MIN. -0.5 -0.5 - -0.5 - - -65 -40 -2000 -200
SAA2003
MAX. +6.5 VDD + 0.5 20 +6.5 20 100 +150 +85 +2000 +200 V V
UNIT
mA V mA A C C V V
MAX.
UNIT
V mA mA A
Inputs FDAI, L3CLK, URDA, SBDIR, SBEF, X256, SLEEP and L3MODE 0 0.7VDD -10 - - - - - - - 50 - 0.3VDD VDD +10 10 V V A pF
Inputs TEST0 and TEST1 LOW level input voltage HIGH level input voltage input pull-down resistance input capacitance VI = VDD 0 0.7VDD - - 0.3VDD VDD - 10 V V k pF
May 1994
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
SYMBOL
PARAMETER
CONDITIONS
MIN. - - 50 - - -
TYP.
MAX.
UNIT
Inputs LTCNT0 and LTCNT1 VIL VIH RI(pu) CI VtLH VtHL Vhys CI VOL VOH CL tr tf LOW level input voltage HIGH level input voltage input pull-up resistance input capacitance VI = 0 V 0 0.7VDD - - - 0.2VDD - - 0.3VDD VDD - 10 V V k pF
Input RESET threshold voltage LOW-to-HIGH threshold voltage HIGH-to-LOW hysteresis voltage input capacitance 0.8VDD - - 10 V V V pF
0.33VDD - - - - - -
Outputs FDCL, FDWS, FDIR, FSYNC, FDAO, MUTEDAC, ATTDAC and DEEMDAC LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 0.4 V to VDD - 0.4 V; CL = 30 pF VDD - 0.4 V to 0.4 V; CL = 30 pF IOL = 4 mA IOH = -4 mA 0.4 V to VDD - 0.4 V; CL = 30 pF VDD - 0.4 V to 0.4 V; CL = 30 pF IOL = 6 mA IOH = -6 mA 0.4 V to VDD - 0.4 V; CL = 50 pF VDD - 0.4 V to 0.4 V; CL = 50 pF IOL = 4 mA IOH = -4 mA 0 VDD - 0.4 - - - 0.4 VDD 30 20 20 V V pF ns ns
Output CLK22 VOL VOH CL tr tf LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 0 VDD - 0.4 - - - - - - - - 0.4 VDD 30 7 7 V V pF ns ns
Output CLK24 VOL VOH CL tr tf LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 0 VDD - 0.4 - - - - - - - - 0.4 VDD 50 7 7 V V pF ns ns
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
SYMBOL Output SYNCDAI VOL VOH CL tr tf
PARAMETER
CONDITIONS
MIN. - - - - -
TYP.
MAX.
UNIT
LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time
IOL = 4 mA IOH = -4 mA 0.4 V to VDD - 0.4 V; CL = 40 pF VDD - 0.4 V to 0.4 V; CL = 40 pF IOL = 6 mA IOH = -6 mA 0.4 V to VDD - 0.4 V; CL = 60 pF VDD - 0.4 V to 0.4 V; CL = 60 pF VI = 0 to VDD IOL = 4 mA IOH = -4 mA 0.4 V to VDD - 0.4 V; CL = 30 pF VDD - 0.4 V to 0.4 V; CL = 30 pF VI = 0 to VDD IOL = 4 mA IOH = -4 mA 0.4 V to VDD - 0.4 V; CL = 50 pF VDD - 0.4 V to 0.4 V; CL = 50 pF VI = 0 to VDD
0 VDD - 0.4 - - -
0.4 VDD 40 20 20
V V pF ns ns
Output FS256 VOL VOH CL tr tf ILI VOL VOH CL tr tf ILI VOL VOH CL tr tf ILI LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 3-state leakage current 0 VDD - 0.4 - - - -10 - - - - - - - - - - - - - - - - - - 0.4 VDD 60 7 7 +10 V V pF ns ns A
Output SD2 LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 3-state leakage current 0 VDD - 0.4 - - - -10 0.4 VDD 30 20 20 +10 V V pF ns ns A
Output IECOP LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 3-state leakage current 0 VDD - 0.4 - - - -10 0.4 VDD 50 20 20 +10 V V pF ns ns A
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
SYMBOL
PARAMETER
CONDITIONS
MIN. - - 50 - - - - - -
TYP.
MAX.
UNIT
Inputs/outputs SBDA, SBCL and SBWS VIL VIH RI(pd) CI VOL VOH CL tr tf LOW level input voltage HIGH level input voltage input pull-down resistance input capacitance LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 0.4 V to VDD - 0.4 V; CL = 30 pF VDD - 0.4 V to 0.4 V; CL = 30 pF IOL = 4 mA IOH = -4 mA VI = VDD 0 0.7VDD - - 0 VDD - 0.4 - - - 0.3VDD VDD - 10 0.4 VDD 30 20 20 V V k pF V V pF ns ns
Inputs/outputs SD1, SCK and WS VIL VIH RI(pd) CI VOL VOH CL tr tf LOW level input voltage HIGH level input voltage input pull-down resistance input capacitance LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 0.4 V to VDD - 0.4 V; CL = 50 pF VDD - 0.4 V to 0.4 V; CL = 50 pF IOL = 4 mA IOH = -4 mA VI = VDD 0 0.7VDD - - 0 VDD - 0.4 - - - - - 50 - - - - - - 0.3VDD VDD - 10 0.4 VDD 50 20 20 V V k pF V V pF ns ns
Input/output L3DATA VIL VIH CI VOL VOH CL tr tf LOW level input voltage HIGH level input voltage input capacitance LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 0.4 V to VDD - 0.4 V; CL = 60 pF VDD - 0.4 V to 0.4 V; CL = 60 pF IOL = 4 mA IOH = -4 mA 0 0.7VDD - 0 VDD - 0.4 - - - - - - - - - - - 0.3VDD VDD 10 0.4 VDD 60 20 20 V V pF V V pF ns ns
Input X22IN (external clock) VIL VIH ILI CI LOW level input voltage HIGH level input voltage input leakage current input capacitance 0 0.7VDD -10 - - - - - 0.3VDD VDD +10 10 V V A pF
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
SYMBOL Output X22OUT fxtal gm Gv Cfb CO VIL VIH ILI CI fxtal gm Gv Cfb CO Input X256 fi
PARAMETER
CONDITIONS - 1.5 Gv = gm x RO 3.5 - -
MIN.
TYP. - - - 5 10
MAX.
UNIT
crystal frequency transconductance small signal voltage gain feedback capacitance output capacitance
note 1
22.5792 - - - - - - - -
MHz mS pF pF
Input X24IN (external clock) LOW level input voltage HIGH level input voltage input leakage current input capacitance 0 0.7VDD -10 - - 1.5 Gv = gm x RO 3.5 - - - - - 35 35 0.3VDD VDD +10 10 - - - 5 10 - - - - - pF pF V V A pF
Output X24OUT crystal frequency transconductance small signal voltage gain feedback capacitance output capacitance note 1 24.567 - - - - MHz mS
input frequency
fs = 48 kHz fs = 44.1 kHz fs = 32 kHz
12.288 11.2896 8.192 - -
MHz MHz MHz ns ns
tcH tcL
HIGH time LOW time
CLK22 and CLK24 timing; Fig.27 OUTPUT CLK24 fo tc24H tc24L tr tf fo tc22H tc22L tr tf output frequency HIGH time LOW time rise time fall time CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF - 12 12 - - - 11 11 - - 24.576 - - - - 22.5792 - - - - - - - 7 7 - - - 7 7 MHz ns ns ns ns
OUTPUT CLK22 output frequency HIGH time LOW time rise time fall time MHz ns ns ns ns
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
SYMBOL
PARAMETER
CONDITIONS -
MIN.
TYP. - - - - 20 - - 90 -
MAX.
UNIT
Drive processing interface timing; see Fig.23 tcy tcH tcL td1 td2 tsu1 th1 tsu2 th2 SCK cycle time SCK HIGH time SCK LOW time SBWS and SBDA delay time until SCK LOW SCK delay time until SBWS and SBDA valid SBDA input set-up time before SCK HIGH SBDA input hold time after SCK HIGH set-up time from SCK HIGH until SBEF valid SBEF input hold time after SCK HIGH 1302 651 651 - - - - - - ns ns ns ns ns ns ns ns ns 460 460 20 - 235 30 - 380
Filtered data interface timing; see Fig.21 FDCL, FDWS, FDAI AND FDAO f256 FS256 frequency fs = 48 kHz fs = 44.1 kHz fs = 32 kHz Tc tFH FDCL cycle time FS256 HIGH time fs = 48 kHz fs = 48 kHz; note 2 fs = 44.1 kHz; note 2 fs = 32 kHz; note 2 tFL FS256 LOW time fs = 48 kHz; note 2 fs = 44.1 kHz; note 2 fs = 32 kHz; note 2 td1 tcH tcL th2 td2 FS256 delay time until FDCL transition FDCL HIGH time FDCL LOW time FDWS, FDAO and FSYNC hold time after FS256 HIGH FS256 HIGH delay time until FDWS, FDAO and FSYNC valid FDAI input set-up time before FS256 HIGH FDAI input hold time after FS256 HIGH fs = 48 kHz fs = 48 kHz - - - - 35 38 75 35 38 35 0 143 143 0 0 12.288 11.2896 8.192 325.6 - - - - - - - - - - - - - - - - - - - - - 50 - - - 50 MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns
tsu th1
20 30
- -
- -
ns ns
May 1994
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - - - -
TYP. - -
MAX.
UNIT
Timing characteristics FDIR and SYNCDAI; see Fig.26 tsH td1 td2 td3 td4 td5 SYNCDAI HIGH time internal clock delay time after SYNCDAI LOW external clock delay time after SYNCDAI LOW FDIR delay time before SYNCDAI HIGH external clock delay time before SYNCDAI HIGH internal clock delay time before SYNCDAI HIGH 1280 0 - 280 - 0 ns ns ns ns ns ns
320 - 320 -
Baseband data interface timing characteristics MASTER MODE; SEE FIGS 17 AND 18 Tc tcH tcL td1 th2 td2 tsu th1 SCK cycle time SCK HIGH time SCK LOW time FS256 HIGH delay time until SCK transition WS, SD1 and SD2 hold time after FS256 HIGH FS256 delay time until WS, SD1 and SD2 valid SD1 input set-up time before SCK HIGH SD1 input hold time after SCK HIGH fs = 48 kHz fs = 48 kHz fs = 48 kHz - 143 143 0 0 0 30 0 325.6 - - - - - - - - - - 50 - 50 - - ns ns ns ns ns ns ns ns
SLAVE MODE; SEE FIG.19 Tc tcH tcL tsu th1 th2 td SCK cycle time SCK HIGH time SCK LOW time WS and SD1 inputs set-up time before SCK HIGH WS and SD1 inputs hold time after SCK HIGH SD1 and SD2 outputs hold time after SCK HIGH SCK delay time until SD1 and SD2 outputs valid fs = 48 kHz fs = 48 kHz fs = 48 kHz 325.6 116 116 30 0 66 - - - - - - - - 651.2 - - - - - 223 ns ns ns ns ns ns ns
May 1994
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - - -
TYP. - - - - -
MAX.
UNIT
Timing characteristics master/slave mode transition; see Fig.20 tsH td1 td2 td3 td4 SYNCDAI HIGH time WS and SCK outputs enabled after SYNCDAI LOW WS and SCK outputs disabled before SYNCDAI LOW SD1 output disabled before SYNCDAI HIGH SD1 output enabled after SYNCDAI LOW 1280 140 140 250 790 ns ns ns ns ns
Timing L3 interface; see Fig.24 ADDRESSING MODE tcH tcL td1 tsu th1 th2 td2 td3 L3CLK HIGH time L3CLK LOW time L3MODE LOW delay time until L3CLK HIGH L3DATA input set-up time before L3CLK HIGH L3DATA input hold time after L3CLK HIGH L3CLK HIGH hold time before L3MODE HIGH L3MODE LOW delay time until L3DATA disabled L3MODE HIGH delay time until L3DATA enabled 210 210 190 190 30 190 0 0 - - - - - - - - - - - - - - 50 50 ns ns ns ns ns ns ns ns
May 1994
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SAA2003
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - - - - - - - - - - -
TYP. - - - 50
MAX.
UNIT
DATA MODE; SEE FIG.25 tcH tcL td1 td2 td3 tsu th1 th2 td4 L3CLK HIGH time L3CLK LOW time L3MODE delay time until L3CLK HIGH L3MODE delay time until L3DATA enabled L3MODE delay time until L3DATA valid L3DATA set-up time before L3CLK HIGH L3DATA input hold time after L3CLK HIGH L3DATA output hold time after L3CLK HIGH L3CLK delay time until L3DATA output valid not between data bits 7 and 8 between data bits 7 and 8 th3 td5 tML Notes 1. The crystal frequencies 22.5792 MHz 200 x 10-6 MHz and 24.5760 MHz 200 x 10-6 MHz must track each other in frequency with an accuracy of 200 x 10-6 MHz. For example if the 24.5760 MHz clock is 150 x 10-6 MHz fast, then the range of the 22.5792 MHz clock becomes -50 x 10-6 MHz and +350 x 10-6 MHz 2. Timing values only valid for internally generated FS256. L3CLK HIGH hold time before L3MODE LOW L3MODE LOW delay time until L3DATA output disabled L3MODE LOW time between data words 210 210 190 0 - 190 30 120 - - 190 0 190 ns ns ns ns ns ns ns ns ns ns ns ns ns
380 - - - 360 530 - 50 -
May 1994
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
PACKAGE OUTLINE
SAA2003
handbook, full pagewidth
seating plane
0.1 S
S
12.9 12.3 44 1 34 33 1.2 (4x) 0.8 B
pin 1 index 0.8
11 12 0.40 0.20 10.1 9.9 22
23
0.40 0.20
0.15 M A
1.2 (4x) 0.8
0.15 M B
10.1 9.9
12.9 12.3
X
0.8
A
0.85 0.75 1.85 1.65 0.25 0.05 0.25 0.14 2.10 1.70
MBB944 - 2
detail X
0.95 0.55
0 to 10 o
Dimensions in mm.
Fig.28 Plastic quad flat-pack, 44-pin (short) (QFP44SL).
May 1994
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
SOLDERING Plastic quad flat-packs BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be
SAA2003
applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
May 1994
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA2003
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
The Digital Compact Cassette logo is a registered trade mark of Philips Electronics N.V.
May 1994
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Philips Semiconductors
Preliminary specification
Stereo filter and codec
NOTES
SAA2003
May 1994
41
Philips Semiconductors
Preliminary specification
Stereo filter and codec
NOTES
SAA2003
May 1994
42
Philips Semiconductors
Preliminary specification
Stereo filter and codec
NOTES
SAA2003
May 1994
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Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2327, Fax. (011)829-1849 Canada: INTEGRATED CIRCUITS: Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 601 Milner Ave, SCARBOROUGH, ONTARIO, M1B 1M8, Tel. (0416)292 5161 ext. 2336, Fax. (0416)292 4477 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H., P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., Components Div., 6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)428 6729 India: Philips INDIA Ltd, Components Dept, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: PHILIPS COMPONENTS S.r.l., Viale F. Testi, 327, 20162 MILANO, Tel. (02)6752.3302, Fax. (02)6752 3300. Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5028, Fax. (03)3740 0580 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: Philips Components, 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546. Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)14163160/4163333, Fax. (01)14163174/4163366. Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., Components Division, 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382. Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319. Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors Limited, P.O. Box 65, Philips House, Torrington Place, LONDON, WC1E 7HD, Tel. (071)436 41 44, Fax. (071)323 03 42 United States: INTEGRATED CIRCUITS: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd., P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404, Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BAF-1, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD31 (c) Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
513061/1500/01/pp44 Document order number: Date of release: May 1994 9397 731 40011
Philips Semiconductors

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